A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits
A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits
复制标题
用于单通量量子 (SFQ) 逻辑电路的新型时钟树感知布局方法
DOI：
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
Wai
中科院分区：
文献类型：
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作者：
Ching;Wai
在单通量量子（SFQ）电路中，几乎所有的单元都需要接收时钟信号，这会导致很高的时钟路由开销。此外，SFQ电路的时钟树需要在每个树分支点处插入时钟分离器单元，这使得布局之后接着时钟树合成的常规设计流程对于获得具有低时钟偏斜的高质量时钟树无效。为了解决这些问题，我们提出了一个两阶段的全球布局方法和布局合法化后的布局优化算法。我们的两个阶段的全球布局方法，首先应用一个传统的全球布局算法放置在给定的SFQ电路中的细胞均匀，其次是时钟树合成和时钟分裂器插入，然后执行第二阶段的全球布局，以重新放置原始细胞和时钟分裂器在同一时间。在第二全局布局阶段，使用前瞻合法化技术来展开原始单元和时钟分配器，并且时钟树被重新合成若干次以获得优化的时钟树拓扑，使得时钟分配器与原始电路单元几乎没有重叠。同时对数据信号和时钟信号的总线长进行了优化。在使所有单元的放置合法化之后，可以运行我们的放置细化方法以进一步减少时钟偏差。与以前的国家的最先进的工作相比，平均来说，我们可以减少总的半周长线长和时钟偏差的9%和31%。分别
In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal which incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point which renders the conventional design flow of placement followed by clock tree synthesis ineffective to obtain a high quality clock tree with low clock skew. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by clock tree synthesis and clock splitter insertion, and then performs a second stage of global placement to re-place both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is re-synthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. In addition, the total wirelength of data signals and clock signal is optimized concurrently. After legalizing the placement of all cells, our placement refinement method can be run to further reduce the clock skew. Compared with the previous state-of-the-art work, on average we can reduce the total half-perimeter wirelength and clock skew by 9% and 31%. respectively.