Reconfigurable hardware architecture for saving power consumption on a sensor node
Reconfigurable hardware architecture for saving power consumption on a sensor node
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DOI：
10.1109/issnip.2008.4762022
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发表时间：
2008-12
期刊：
影响因子：
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通讯作者：
Satoshi Tanaka;N. Fujita;Yutaka Yanagisawa;T. Terada;M. Tsukamoto
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文献类型：
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作者：
Satoshi Tanaka;N. Fujita;Yutaka Yanagisawa;T. Terada;M. Tsukamoto
我们提出了使用一个可重构的硬件架构，以减少具有各种传感器和无线通信设施，这是一个自适应功能专业化机制的结果的小型传感器节点的功耗。传统的传感器节点必须具有功能强大的多功能微控制器（MCU）才能满足处理各种应用的要求。然而，这些系统中的大多数仅使用MCU提供的部分功能。换句话说，这样的单元经常为未使用的电路消耗大量的功率。为了避免这种情况，我们建议使用基于现场可编程门阵列（FPGA）而不是MCU的可重构架构，因为该阵列动态地将电路更改为仅用于应用程序所需计算的最佳电路。此外，我们实现了一个原型系统做我们提出的机制的初步评估。在这次评估中，我们所提出的可重构架构的性能与传统的架构，使用处理时间和功耗进行比较。实验结果表明，该机制在不减少处理时间的情况下，降低了传感器节点的功耗，延长了节点的生存时间。
We propose the use of a reconfigurable hardware architecture to reduce the power consumption of small sensor node that has various sensors and wireless communication facilities, that were the result of an adaptive function specialization mechanism. Traditional sensor nodes must have had a powerful and multi functional Micro-Controller Unit (MCU) to satisfy the requirements for processing any kinds of application. However, most of these systems only use a part of the functions provided by an MCU. In other words, such a unit often consumes a great dead of power for unused circuits. To avoid this situation, we propose the use of a reconfigurable architecture based on a Field Programmable Gate Array (FPGA) instead of an MCU because this array dynamically changes the circuit to the optimal one that is just used for the calculation required by an application. Moreover, we implemented a prototype system to do a preliminary evaluation of our proposed mechanism. In this evaluation, we show the performance of our proposed reconfigurable architecture by comparison with traditional architecture that uses processing time and power consumption. The experimental result shows that our proposed mechanism reduces enough power of its sensor nodes to prolong the lifetime of nodes without decreasing the processing time.