Digital Background Correction for Channel Mismatch and Third-Order Nonlinearity of TI-ADCs with VCOs
Digital Background Correction for Channel Mismatch and Third-Order Nonlinearity of TI-ADCs with VCOs
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针对具有 VCO 的 TI-ADC 的通道失配和三阶非线性进行数字背景校正
DOI：
10.1109/apccas51387.2021.9687812
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发表时间：
2021
期刊：
影响因子：
--
通讯作者：
Takao Kihara
中科院分区：
文献类型：
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作者：
Hiroyuki Ichida;Keiichi Kaneko;Antoine Bossard;Antoine Bossard;Takao Kihara
时间交错模数转换器（TI-ADC）可以通过使用压控振荡器（VCO）来有效地将射频（RF）（几千兆赫）信号转换为具有中等分辨率的数字信号。然而，该ADC分别由于通道失配和VCO增益的非线性而遭受混叠信号以及谐波失真（HD）和互调（IM）产物。我们首先提出了一种数字背景校正，以减少失配混叠信号和三阶HD和IM产品的四通道TI ADC与VCO。我们的方法利用复杂的和抽取的信号，从一个直接的RF接收机，和自适应滤波器与这些信号的互相关函数。然后，我们实现了24位浮点运算的校正电路，以平衡精度和功耗。仿真结果表明，在采样频率为3,680 MHz的TI ADC中，该校正将双音无杂散动态范围（SFDR）从54.8 dB提高到66.7 dB，采用65 nm CMOS工艺设计的电路工作功率为4.3 mW，速率为57.5 MS/s。
A time-interleaved analog-to-digital converter (TI-ADC) can efficiently convert radio-frequency (RF), a few gigahertz, signals into digital ones with medium resolution by using voltage controlled oscillators (VCOs). This ADC, however, suffers from aliasing signals, and harmonic distortion (HD) and intermodulation (IM) products owing to the channel mismatches and the nonlinearity of the VCO gain, respectively. We first present a digital background correction to reduce the mismatch aliasing signals and the third-order HD and IM products of four-channel TI-ADCs with VCOs. Our method utilizes the complex and decimated signals, sent from a direct-RF receiver, and adaptive filters with cross-correlation functions of these signals. Then, we implement the correction circuit with 24-bit floating point arithmetic to compromise between the accuracy and power consumption. Simulations show that the correction improves the two-tone spurious-free dynamic range (SFDR) of a TI-ADC with a sampling frequency of 3,680 MHz from 54.8 dB to 66.7 dB and the circuit designed with a 65-nm CMOS technology operates at 4.3 mW and a rate of 57.5 MS/s.