Small Memory Footprint Neural Network Accelerators
Small Memory Footprint Neural Network Accelerators
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DOI：
10.1109/isqed.2019.8697641
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发表时间：
2019-03
期刊：
影响因子：
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通讯作者：
Kenshu Seto;Hamid Nejatollahi;Jiyoung An;Sujin Kang;N. Dutt
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文献类型：
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作者：
Kenshu Seto;Hamid Nejatollahi;Jiyoung An;Sujin Kang;N. Dutt
深度神经网络（DNN）加速器提供通常用于边缘设备的高精度数据识别。然而，资源受限的边缘设备通常具有较小的外形尺寸和有限的资源，而DNN加速器需要大量的计算和内存占用。特别是，深度神经网络的内存需求成为在小尺寸设备上实现加速器的主要瓶颈。为了减少内存占用，融合层卷积神经网络（CNN）加速器被提出用于图像识别网络。融合层CNN通过在片上执行一组CNN层，并用层间的片内存储器访问取代片外存储器访问，减少片外存储器访问。虽然融合层cnn减少了片外存储器的访问，但它们仍然需要大量的片内存储器，占用了大量的芯片面积，这使得它们在小尺寸器件上的实现不切实际。我们通过提出一种设计技术来解决这个问题，该技术可以生成具有小内存足迹的融合cnn加速器，并通过案例研究展示其潜力。
Deep Neural Network (DNN) accelerators provide high-accuracy data recognition that are commonly used in edge devices. However, resource constrained edge devices usually have small form factors and limited amounts of resources, whereas DNN accelerators require large amounts of computations and memory footprint. In particular, the memory requirements of DNNs become a major bottleneck for realization of accelerators on small footprint devices. To reduce the memory footprint, fused-layer convolutional neural network (CNN) accelerators have been proposed for image recognition networks. Fused-layer CNNs reduce off-chip memory accesses by executing a set of CNN layers on-chip and by replacing the off-chip memory accesses with on-chip memory accesses between the layers. Although fused-layer CNNs reduce the off-chip memory accesses, they still require large amounts of on-chip memories that occupy significant chip area, making impractical their realization on small footprint devices. We address this problem by proposing a design technique that generates fused-CNN accelerators with small memory footprints, demonstrate its potential via a case study.