Nanomagnetic logic clocked in the MHz regime

Nanomagnetic logic clocked in the MHz regime
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纳米磁性逻辑时钟频率为 MHz

DOI:
10.1109/essderc.2013.6818872
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发表时间:
2013
期刊:
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)
影响因子:
--
通讯作者:
D. Schmitt
D. Schmitt
中科院分区:
--
文献类型:
--
作者:
M. Becherer;J. Kiermaier;S. B. Gamm;I. Eichwald;G. Csaba;D. Schmitt

文献摘要

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恒磁纳米逻辑是一种利用铁磁体的局部磁化和边缘场来存储和处理信息的计算概念。到目前为止,pNML设备仅在毫秒级时间尺度上运行。在这项工作中,pNML磁体由平面片上电感器以100 kHz至10 MHz的频率进行计时。确定了单个磁体的固有开关场(SF)和SF分布(SFD)。阿克里尼乌斯方程用于模拟SFD。此外,磁功率时钟,实现了一个片上电感与铁磁包层,提出并分析了有限元模拟。利用所提取的数据,给出了缩放pNML计算系统的功率密度的估计。
Perpendicular Nanomagnetic Logic (pNML) is a computing concept, where the local magnetization and fringing fields of ferromagnets are used to store and process information. So far, pNML devices have been exclusively operated at millisecond time scales. In this work, pNML magnets are clocked by a planar on-chip inductor at frequencies ranging from 100 kHz to 10 MHz. The inherent switching field (SF) and SF distribution (SFD) of an individual magnet is determined. An Arrhenius equation is used in order to model the SFD. Furthermore, a magnetic power-clock, implemented by an on-chip inductor with ferromagnetic cladding, is proposed and analyzed by finite element simulations. With the extracted data, an estimate of the power density of a scaled pNML computing system is given.