Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration
Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration
复制标题
通过动态部分重新配置实现并行加速器的低开销容错
DOI：
10.1109/fpl.2014.6927447
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
P. Cheung
中科院分区：
文献类型：
--
作者：
James J. Davis;P. Cheung
虽然允许制造日益复杂和高效的电路，但晶体管的缩小和每器件数量的扩展具有重大缺点：主要是增加了变化、退化和故障敏感性。因此，未来越来越多的电子系统必须在设计时考虑容错，以确保产量、可靠性和寿命保持在可接受的高水平。许多常用的运算符都适合进行修改，从而以较低的面积开销实现数据路径错误检测功能。 FPGA 具有独特的优势，由于其动态可重配置性，在结合故障避免机制时可以进一步节省面积。在本文中，我们研究了在测试平台上实现硬件-软件容错所涉及的实用性和成本：硬件中的并行矩阵乘法加速器，带有软件中的控制器，在 Xilinx Zynq 片上系统上运行。 “螺栓固定”错误检测逻辑和软件触发的路由重新配置的组合可在运行时提供低开销的数据路径容错能力。实现快速而准确的故障诊断以及较低的硬件（面积）、软件（配置存储）和性能损失。
While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of fault tolerance will have to be given to increasing numbers of electronic systems in the future to ensure yields, reliabilities and lifetimes remain acceptably high. Many commonly implemented operators are suited to modification resulting in datapath error detection capabilities with low area overheads. FPGAs are uniquely placed to allow further area savings to be made when incorporating fault avoidance mechanisms thanks to their dynamic reconfigurability. In this paper, we examine the practicalities and costs involved in implementing hardware-software fault tolerance on a test platform: a parallel matrix multiplication accelerator in hardware, with controller in software, running on a Xilinx Zynq system-on-chip. A combination of `bolt-on' error detection logic and software-triggered routing reconfiguration serve to provide low-overhead datapath fault tolerance at runtime. Rapid yet accurate fault diagnoses along with low hardware (area), software (configuration storage) and performance penalties are achieved.