A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)
A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)
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DOI：
10.1109/isscc.2004.1332634
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发表时间：
2004-09
期刊：
影响因子：
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通讯作者：
D. Mizoguchi;Y.B. Yusof;N. Miura;T. Sakura;T. Kuroda
中科院分区：
文献类型：
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作者：
D. Mizoguchi;Y.B. Yusof;N. Miura;T. Sakura;T. Kuroda
以金属螺旋电感为接口，设计了一种堆叠芯片无线总线。开发了非归零信令收发电路。堆叠在300PU/m距离的测试芯片以高达1.2 Gb/S/针的数据速率通信。采用0.35/SPL Mu/m工艺制作，TX和RX功耗分别为43 mW和2.5 mW。
A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300/spl mu/m communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35/spl mu/m CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.