System-on-a-chip test-data compression and decompression architectures based on Golomb codes
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
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DOI：
10.1109/43.913754
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发表时间：
2001-03-01
影响因子：
2.9
通讯作者：
Chakrabarty, K
中科院分区：
文献类型：
--
作者：
Chandra, A;Chakrabarty, K
本文提出了一种基于可变到可变长度的Golomb编码的测试数据压缩方法和解压缩架构，该方法特别适用于在片上系统（SoC）中对嵌入式内核的预计算测试集进行编码。Golomb编码测试数据的主要优点包括非常高的压缩率、可分析预测的压缩结果以及低成本和可扩展的片上解码器。新颖的交错解压缩架构允许使用单个自动测试设备输入输出通道同时测试SoC中的多个核心。我们通过将其应用于电路与系统国际研讨会的基准电路和两个工业生产电路来证明所提出方法的有效性。我们还使用分析和实验的方法来强调Golomb码相对于游程码的优越性。
We present a new test-data compression method and decompression architecture based on variable-to-variable-length Golomb codes, The proposed method is especially suitable for encoding precomputed test sets for embedded cores in a system-on-a-chip (SoC), The major advantages of Golomb coding of test data include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder, In addition, the novel interleaving decompression architecture allows multiple cores in an SoC to be tested concurrently using a single automatic test equipment input-output channel. We demonstrate the effectiveness of the proposed approach by applying it to the Internaional Symposium on Circuits and Systems' benchmark circuits and to two industrial production circuits. We also use analytical and experimental means to highlight the superiority of Golomb codes over run-length codes.