An Analog Front-End Chip With Self-Calibrated Input Impedance for Monitoring of Biosignals via Dry Electrode-Skin Interfaces
An Analog Front-End Chip With Self-Calibrated Input Impedance for Monitoring of Biosignals via Dry Electrode-Skin Interfaces
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具有自校准输入阻抗的模拟前端芯片，用于通过干电极-皮肤接口监测生物信号
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发表时间：
2017
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通讯作者：
M. Onabajo
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作者：
Chun;Seyed Alireza Zahrai;Kainan Wang;Li Xu;Ibrahim Farah;M. Onabajo
本文演示了一种输入阻抗升压方法，该方法是为长期监测脑电信号而开发的。为了消除电极电缆和印刷电路板输入电容的不利影响，设计了一种采用负电容产生反馈（NCGFB）技术的仪表放大器。当输入端的等效电容高达150 pF时，NCGFB可在50 Hz时将测得的阻抗从低于40 M<inline-formula><tex-math notation="LaTeX">$Omega $</tex-math></inline-formula>提升至高于500 M<inline-formula><tex-math notation="LaTeX">$Omega $</tex-math></inline-formula>。原型芯片包括一个自动校准系统，可通过片上测试信号生成、测量和NCGFB的自动数字控制自适应地增强输入阻抗。该信号路径采用130 nm CMOS工艺，由仪表放大器、低通陷波滤波器和可变增益放大器组成，组合增益范围为66-93 dB，总功耗为42<inline-formula><tex-math notation="LaTeX">$mu$</tex-math></inline-formula> W。前端带宽范围为0.5-48 Hz，整个带宽内的集成输入参考噪声为3.75<inline-formula><tex-math notation="LaTeX">$mu$</tex-math></inline-formula> V<sub>rms</sub>。测得的三阶谐波失真分量至少比基波信号电平低57 dB。在10 Hz时，共模抑制比为77.6 dB，电源抑制比为74 dB。当激活时，辅助测试信号生成和校准电路消耗542<inline-formula><tex-math notation="LaTeX">$mu$</tex-math></inline-formula> W的功率。
This paper demonstrates an input impedance boosting method that was developed for long-term monitoring of electroencephalography signals. An instrumentation amplifier was designed with a negative capacitance generation feedback (NCGFB) technique to cancel the adverse effects of input capacitances from electrode cables and printed circuit boards. The NCGFB boosts the measured impedance from below 40 M<inline-formula> <tex-math notation="LaTeX">$Omega $ </tex-math></inline-formula> to above 500 M<inline-formula> <tex-math notation="LaTeX">$Omega $ </tex-math></inline-formula> at 50 Hz when the equivalent capacitance at the inputs is up to 150 pF. The prototype chip includes an automatic calibration system to adaptively enhance the input impedance through on-chip test signal generation, measurement, and the automatic digital control of the NCGFB. Consisting of an instrumentation amplifier, a low-pass notch filter, and a variable gain amplifier in 130-nm CMOS technology, the signal path has a combined gain range of 66–93 dB with a total power consumption of 42 <inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W. The front-end bandwidth covers 0.5–48 Hz, and its integrated input-referred noise over the bandwidth is 3.75 <inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>V<sub>rms</sub>. The measured third-order harmonic distortion component is at least 57 dB below the fundamental signal level. A common-mode rejection ratio of 77.6 dB and a power supply rejection ratio of 74 dB were measured at 10 Hz. When activated, the auxiliary test signal generation and calibration circuits consume a power of 542 <inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math></inline-formula>W.