A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch
A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch
复制标题
具有高 DAC 失配容限的高分辨率 Delta-Sigma D/A 转换器架构
DOI：
10.1109/iscas.2018.8351088
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
Yanquan Luo
中科院分区：
文献类型：
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作者：
Yanquan Luo
提出了一种Δ-Σ调制器架构，其减少了多位Δ-Σ DAC中的数模转换器（DAC）非线性的影响。通过级联和确定性抖动，多位DAC仅处理小信号，因此可以保持大的动态范围;通过在多位DAC处理之前抑制带外噪声，较少的整形噪声被非线性DAC互调，因此降低了噪声基底的升高。该架构提供了一种在低过采样率（OSR）下实现高分辨率多位Δ-Σ DAC的实用方法。MATLAB中的系统级仿真表明，在OSR = 10时，DAC元件失配为0.2%（标准差）时，平均有效位数为14.5位。
A delta-sigma modulator architecture reducing the impact of the digital-to-analog converter (DAC) non-linearity in a multi-bit delta-sigma DAC is presented. By cascading and deterministic dithering, only small signals are processed by the multi-bit DAC, thus a large dynamic range can be maintained; by suppressing the out-of-band noise before being processed by the multi-bit DAC, less shaped-noise gets inter-modulated by the non-linear DAC, thus the raise of noise floor is reduced. The proposed architecture provides a practical way to implement a high-resolution multi-bit delta-sigma DAC at low over-sampling rate (OSR). System level simulations in MATLAB show that an average ENOB=14.5-bits can be achieved with 0.2% (standard deviation) DAC element mismatch at OSR = 10.
双截断Sigma Delta D/A转换器的实现
DOI：
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发表时间：
1992
期刊：
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems
影响因子：
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作者：
X. Xu;G. Temes;R. Schreier
通讯作者：
R. Schreier