3DVLSI with CoolCube process: An alternative path to scaling
3DVLSI with CoolCube process: An alternative path to scaling
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采用 CoolCube 工艺的 3DVLSI：扩展的替代途径
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
M. Vinet
中科院分区：
文献类型：
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作者：
P. Batude;C. Fenouillet;L. Pasini;V. Lu;F. Deprat;L. Brunet;B. Sklénard;F. Piegas;M. Cassé;B. Mathieu;O. Billoint;G. Cibrario;O. Turkyilmaz;H. Sarhan;S. Thuries;L. Hutin;S. Sollier;J. Widiez;L. Hortemel;C. Tabone;M.;B. Previtali;N. Rambal;F. Ponthenier;J. Mazurier;R. Beneyton;M. Bidaud;E. Josse;E. Petitprez;O. Rozeau;M. Rivoire;C. Euvard;A. Seignard;F. Fournel;L. Benaissa;P. Coudrain;P. Leduc;J. Hartmann;P. Besson;S. Kerdilès;C. Bout;F. Nemouchi;A. Royer;C. Agraffeil;Gérard Ghibaudo;T. Signamarcheix;Michel Haond;F. Clermidy;O. Faynot;M. Vinet
具有 CoolCube™ 集成的 3D VLSI 允许垂直堆叠多层器件，其独特的连接通孔密度超过 100 万/mm2。这会导致密度增加，而无需与晶体管缩放相关的额外成本，同时由于线长减少而受益于功率和性能的提高。 CoolCube™ 技术可实现高性能顶部晶体管，其热预算 (TB) 与底部 MOSFET 完整性兼容。关键促成因素是通过固相外延 (SPE) 或纳秒激光退火进行掺杂剂激活、低温外延、低 k 间隔物和直接键合。关于底部 MOSFET 能够承受的最大 TB 级（高温但持续时间短）的新数据为顶部 MOSFET 工艺优化提供了新的机会。
3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.