Lattice-Traversing Design Space Exploration for High Level Synthesis
Lattice-Traversing Design Space Exploration for High Level Synthesis
复制标题
用于高级综合的格子遍历设计空间探索
DOI：
10.1109/iccd.2018.00040
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
L. Pozzi
中科院分区：
文献类型：
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作者：
Lorenzo Ferretti;G. Ansaloni;L. Pozzi
本文描述了一种设计空间探索方法的高级综合（HLS）框架。HLS工具的输入是对预期硬件功能的描述（通常是C/C++），以及一组指定其实现的优化指令，从而允许生成具有广泛变化的性能和所需资源的许多设计变体。然而，指令和性能/成本之间的关系并不简单，并且受到特定应用特性的高度影响。设计师面临的一个主要挑战是为指令定义有效的值，同时避免耗时且通常不可行的详尽探索。我们在这里解决它，提出了一种新的HLS探索方法，采用点阵表示的设计空间，和它的导航方法。我们基于我们的策略的观察，帕累托实现共享低方差之间的配置。因此，我们指导HLS指令的选择，最大限度地减少新的候选解决方案的方差，相对于已经访问过的最佳性能。通过只需要在晶格空间中进行局部搜索，我们的方法可以优雅地扩展到复杂的设计。它的结果在密切接近的真实的帕累托前沿，同时需要一个较低的工作量和较少的合成运行相对于现有的方法。
This paper describes a design space exploration methodology for High Level Synthesis (HLS) frameworks. Inputs of HLS tools are a description (usually in C/C++) of the functionality of an intended hardware, and a set of optimisation directives that specify its implementation, hence allowing the generation of many design variants with widely varying performance and required resources. The relationship between directives and performance/cost is nonetheless not straightforward, and highly influenced by application-specific characteristics. A major challenge facing designers is then to define effective values for the directives while avoiding time-consuming – and often infeasible – exhaustive explorations. We herein address it by proposing a novel HLS exploration approach which employs a lattice representation of the design space, and a methodology for its navigation. We base our strategy on the observation that Pareto-implementations share a low variance among their configurations. We therefore guide the selection of HLS directives minimising the variance of new candidate solutions, with respect to the best performing ones that have already been visited. By only requiring local searches in the lattice space, our methodology gracefully scales to complex designs. It results in close approximations of the real Pareto frontier, while requiring a lower workload and fewer synthesis runs with respect to existing approaches.