A 228 $\mu$ W 750 MHz BPSK Demodulator Based on Injection Locking
A 228 $\mu$ W 750 MHz BPSK Demodulator Based on Injection Locking
复制标题
基于注入锁定的 228 $mu$ W 750 MHz BPSK 解调器
DOI：
10.1109/jssc.2010.2090611
复制
发表时间：
2011
影响因子：
5.4
通讯作者：
Yang Xu
中科院分区：
文献类型：
--
作者：
Qiang Zhu;Yang Xu
本文介绍了一种基于注入锁定振荡器的超低功耗BPSK解调器。采用两个二次谐波检波器将BPSK信号转换为ASK信号，再由包络检波器解调到基带。对于sub-GHz应用，使用环形振荡器来实现ADC，以实现紧凑的芯片面积和超低功耗。该解调器的误码率（BER）分析表明，由于ILO的相位噪声，解调比特的极性翻转错误。原型芯片采用65 nm CMOS工艺制作，功耗228 μW，芯片面积0.014 mm 2。测量结果表明，该解调器对750 MHz 5 Mb/S差分BPSK信号的解调灵敏度为-43 dBm。理论BER分析已被验证与错误的翻转观察到的测量和其概率接近的预测。
An ultra-low-power BPSK demodulator based on injection locked oscillators (ILOs) is introduced in this paper. Two second harmonic ILOs are employed to convert BPSK signals to ASK signals, which are then demodulated by an envelope detector to baseband. For sub-GHz applications, the ILOs are implemented using ring oscillators to allow compact chip area and ultra-low power dissipation. Bit error rate (BER) analysis of this demodulator indicates erroneous polarity flipping of demodulated bits due to phase noise of ILO. The prototype chip is fabricated in a 65 nm CMOS technology that consumes 228 μW of power and occupies 0.014 mm2 of die area. Measurement results reveal the demodulation of 750 MHz 5 Mb/S differential BPSK signal with sensitivity of -43 dBm. Theoretical BER analysis has been verified with erroneous flipping observed in the measurement and its probability close to the prediction.