Design and implementation of OFDM timing synchronization with repeated-structured training sequence based on FPGA
Design and implementation of OFDM timing synchronization with repeated-structured training sequence based on FPGA
复制标题
基于FPGA的重复结构训练序列OFDM定时同步设计与实现
DOI：
10.1109/icsess.2014.6933757
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Shuguang Gao
中科院分区：
文献类型：
--
作者：
Ye Tian;Ruonan Wang;Qingfan Li;Lishi Liu;Shuguang Gao
在OFDM同步算法中，基于重复结构化训练序列的算法因其结构简单、频率估计精度高而得到广泛应用。提出一种以FPGA作为硬件平台的重复结构训练序列的OFDM定时同步的实现方法。该设计分为三个部分。第一部分包括m序列生成器模块和用于构造训练序列的FIFO模块的实现。第二个用于在数据符号帧前面添加训练结构生成，并在训练符号前面插入噪声序列。最后一部分用于查找定时同步的位置。我们通过 Verilog-HDL 编码并使用 Xilinx ISE 13.3 软件平台提供的 IP 核来执行所有这些设计。最后将这些电路下载到基于Xilinx XC6VLX240T-1FF1156芯片的FPGA开发板ML-605中。实验结果表明，定时位置落在循环前缀(CP)序列的范围内，说明了所设计方案的正确性和有效性。
Among the OFDM synchronization algorithms, the algorithm based on repeated structured training sequence is widely used because of its simple structure and high accuracy of frequency estimation. An implementation method of OFDM timing synchronization with repeated-structured training sequence is presented in this paper, which uses FPGA as a hardware platform. There are three parts in this design. The first part includes the implementation of m sequence generator module and FIFO module used to construct the training sequence. The second one is used to add the training structure generation in front of the Data symbol frame and to insert noise sequence in front of training symbol. The last part is used to find the position of the timing synchronization. We execute all of these designs by coding in Verilog-HDL and using IP Cores supplied by Xilinx ISE 13.3 software platforms. At last, all these circuits are downloaded to FPGA development board ML-605 based on XC6VLX240T-1FF1156 chip of Xilinx. Experiment results show that the timing position fall in the range of the cyclic prefix (CP) sequence, which indicates correctness and validity of the scheme designed.