Analysis of Linear-Doped Si/SiC Power LDMOSFETs Based on Device Simulation
Analysis of Linear-Doped Si/SiC Power LDMOSFETs Based on Device Simulation
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DOI：
10.1109/ted.2016.2550865
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发表时间：
2016-06-01
影响因子：
3.1
通讯作者：
Gammon, Peter M.
中科院分区：
文献类型：
--
作者：
Chan, Chunwa;Mawby, Philip A.;Gammon, Peter M.
提出了一种用于高温应用的600 V硅/碳化硅（Si/SiC）横向扩散MOSFET的设计和优化方法，其漂移区具有线性掺杂分布。提出的结构具有嵌入式绝缘体上硅（SOI）布局，通过该布局，传统的SOI梯度掺杂理论可以应用于Si/SiC架构。一个SOI对应的引入作为一个基准和建模旁边的拟议结构。它们之间的比较表明，它们具有几乎相同的关断状态和击穿特性，在450 V以上出现显著的隧穿泄漏分量。在导通状态下，Si/SiC器件具有更高的电阻，但热阻低得多，导致更少的自加热和更高的可靠性。
This paper presents the design and optimization of a 600 V silicon-on-silicon carbide (Si/SiC) laterally diffused MOSFET with linear doping profile in the drift region for high-temperature applications. The proposed structure has an embedded silicon-on-insulator (SOI) layout through which the traditional graded doping theory for SOI can be applied in the Si/SiC architecture. An SOI counterpart is introduced as a benchmark and modeled alongside the proposed structure. Comparisons between them show that they have the near-identical OFF-state and breakdown characteristics, with a significant tunneling leakage component emerging above 450 V. In the ON state, the Si/SiC device has higher electrical resistance but much lower thermal resistance, leading to less self-heating and higher reliability.