Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption
Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption
复制标题
FPGA 中的低功耗数字设计：研究使用低电源电压在 FPGA 中实现的流水线架构以降低功耗
DOI：
10.1109/iscas.2000.857496
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发表时间：
2000
期刊：
影响因子：
--
通讯作者：
J. Danger
中科院分区：
文献类型：
--
作者：
A. D. García;W. Burleson;J. Danger
一些使用尽可能低的电源电压并进行架构优化的超大规模集成电路低功耗操作技术表明，即使我们增加硅面积，也可以节省功耗。在本文中，我们提出了一种基于低电源电压工作的流水线架构来降低 FPGA 功耗的策略。
Some techniques for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization have shown that we can save power even if we increase silicon area. In this paper we present a strategy to reduce power consumption in FPGAs based on pipeline architectures working with a low supply voltage.