Address-Value Decoupling for Early Register Deallocation
Address-Value Decoupling for Early Register Deallocation
复制标题
地址值解耦以实现早期寄存器释放
DOI：
10.1109/icpp.2006.20
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
Aneesh Aggarwal
中科院分区：
文献类型：
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作者：
D. Balkan;J. Sharkey;D. Ponomarev;Aneesh Aggarwal
我们提出了一系列积极的寄存器释放机制，以减少寄存器文件压力并增加超标量微处理器所利用的并行性。我们的技术基于一个关键的观察，即寄存器值可以暂时与寄存器标识符解耦。具体来说，即使物理寄存器被释放，该值在寄存器中仍然可用，并且可以由相关指令读取，直到寄存器被覆盖。在这些情况下，我们可以有效地重叠生成的寄存器值的消耗和将同一寄存器重新分配给它的指令的部分处理。在本文中，我们提出了地址值解耦思想的几种实现，并讨论了它们对性能的影响。我们最积极的方案在模拟 SPEC 2000 基准测试中实现了 14.6% 的平均 IPC 加速
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our techniques are based on a key observation that a register value can be temporarily decoupled from the register identifier. Specifically, even if a physical register is deallocated, the value is still available in the register and can be read by the dependent instructions until the register is overwritten. In these situations, we can effectively overlap the consumption of the produced register value and partial processing of the instruction that gets the same register reassigned to it. In this paper, we propose several realizations of the address-value decoupling idea and discuss their implications on the performance. Our most aggressive scheme achieves an average IPC speedup of 14.6% across simulated SPEC 2000 benchmarks
通过位分区实现小型、快速且低功耗的寄存器文件
DOI：
--
发表时间：
2005
期刊：
Proc. of HPCA-11
影响因子：
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作者：
M.Kondo;H.Nakanura
通讯作者：
H.Nakanura