High performance CMOS dual supply level shifter for a 0.5V input and 1V output in standard 1.2V 65nm technology process
High performance CMOS dual supply level shifter for a 0.5V input and 1V output in standard 1.2V 65nm technology process
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高性能 CMOS 双电源电平转换器，采用标准 1.2V 65nm 技术工艺，提供 0.5V 输入和 1V 输出
DOI：
10.1109/iscit.2009.5340988
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发表时间：
2009
期刊：
影响因子：
--
通讯作者：
S. Nooshabadi
中科院分区：
文献类型：
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作者：
José C. García;J. Montiel;S. Nooshabadi
本文介绍了一种高效CMOS电平移位器的设计。不像许多最近的电平移位器，建议的qc电平移位器不使用自举电容器，以尽量减少有效面积。在65 nm CMOS工艺上实现时，在大容性负载（2 pF）条件下，qc电平移位器的有效面积（94%）和能量延迟积（21.4%）均低于基准自举电平移位器（ts-电平移位器）。与传统的移位器（C电平移位器）相比，相应的减少分别为9.5%和55%。此外，与ts电平移位器相比，qc电平移位器具有非常小的有效输入电容，因为它不需要连接到其输入的自举电容器。
This paper presents the design of a highly efficient CMOS level shifter qc-level shifter. Unlike many recent level shifters, the proposed qc-level shifter does not use bootstrap capacitors to minimize active area. When implemented on a 65nm CMOS technology, under the large capacitive loading condition (2pF), qc-level shifter has a lower active area (94%), and energy-delay product (21.4%) than the reference bootstrap level shifter circuit (ts-level shifter). In comparison to a conventional shifter (c-level shifter)the corresponding reductions are 9.5% and 55%, respectively. Also qc-level shifter has very small effective input capacitance in comparison with ts-level shifter as it does not need a bootstrap capacitor connected to its input.