Analysis and design of an X-band-to-W-band CMOS active multiplier with improved harmonic rejection
Analysis and design of an X-band-to-W-band CMOS active multiplier with improved harmonic rejection
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DOI：
10.1109/tmtt.2013.2252914
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发表时间：
2013-04
影响因子：
4.3
通讯作者：
N. Mazor;E. Socher
中科院分区：
文献类型：
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作者：
N. Mazor;E. Socher
对 CMOS 晶体管中的三次谐波电流生成进行了建模和分析，包括毫米波 (mm-wave) 倍频器应用中的大信号限幅和高频滚降的影响。使用该模型并引入谐波抑制技术，设计并表征了使用 65 nm CMOS 工艺实现的从 X 频段到 W 频段的宽带 8.5 dBm 输出功率 x9 倍频器。使用六个变压器耦合差分级，两个三倍器级、一个Ka波段放大器和一个三级W波段功率放大器(PA)。该电路在 91.8 GHz 时达到 8.5 dBm 的饱和输出功率，在 88 至 99.5 GHz 范围内带宽为 12.2%。在所有带宽上均能出色地抑制不需要的谐波，抑制效果优于 31 dBc。该核心设计尺寸仅为 390 μm × 675 μm，1.2/2.4V 电源功耗为 438 mW。
Third-harmonic current generation in a CMOS transistor is modeled and analyzed including the effects of large-signal clipping and high-frequency roll-off for the application of millimeter-wave (mm-wave) frequency multipliers. Using the model and introducing harmonic rejection techniques, a wideband 8.5-dBm output-power x9 frequency multiplier from X-band to W-band implemented using a 65-nm CMOS process is designed and characterized. Six transformer coupled differential stages are used, two tripler stages, a Ka-band amplifier, and a three-stage W-band power amplifier (PA). The circuit reaches a saturated output power of 8.5 dBm at 91.8 GHz with a 12.2% bandwidth from 88 to 99.5 GHz. Excellent suppression of unwanted harmonics is achieved with better than 31 dBc across all bandwidth. The core design occupies only 390 μm × 675 μm and consumes 438 mW from a 1.2-/2.4-V supply.