SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits
SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits
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DOI：
10.1093/ietfec/e88-a.4.1038
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发表时间：
2005-04
期刊：
影响因子：
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通讯作者：
Katsunori Tanaka;S. Yamashita;Y. Kambayashi
中科院分区：
文献类型：
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作者：
Katsunori Tanaka;S. Yamashita;Y. Kambayashi
在本文中，我们提出了基于查找表（基于 LUT）现场可编程门阵列（FPGA）电路中有效连线添加的条件，以及利用有效连线添加的优化过程。每条线都有不同的特性，例如延迟和功耗。因此，用许多非关键线替换对电路性能至关重要的一根线，即多加一除（m-for-1）是足够有用的。然而，基于LUT的FPGA电路的基于待区分函数对集合(SPFD)的传统逻辑优化方法并没有利用m-for-1操作，而仅执行简单的替换和去除，即分别进行一加一去除(1-for-1)操作和不加一去除(0-for-1)操作。由于每个LUT可以针对指定数量的输入变量实现任意内部功能，因此在逻辑设计层面上不存在简单连线相加的充分条件。此外，一般来说，简单添加一根线对去除另一根线没有影响，导出非简单且有效的线添加条件很重要。我们发现基于 SPFD 的条件，即导线添加可能使另一根导线变得冗余或可替换，并利用这种有效的导线添加开发了一种优化程序。根据实验结果，当我们专注于基于LUT的FPGA电路的延迟减少时，我们的方法比初始电路减少了24.2%的延迟，而传统的基于SPFD的逻辑优化和增强的全局重新布线分别减少了14.2%和18.0%。因此，本文提出的方法足够实用，有望提高电路性能。
In this paper, we present the condition for the effective wire addition in Look-Up-Table-based (LUT-based) field programmable gate array (FPGA) circuits, and an optimization procedure utilizing the effective wire addition. Each wire has different characteristics, such as delay and power dissipation. Therefore, the replacement of one critical wire for the circuit performance with many non-critical ones, i.e., many-addition-for-one-removal (m-for-1) is sufficiently useful. However, the conventional logic optimization methods based on sets of pairs of functions to be distinguished (SPFDs) for LUT-based FPGA circuits do not make use of the m-for-1 manipulation, and perform only simple replacement and removal, i.e., the one-addition-for-one-removal (1-for-1) manipulation and the no addition-for-one-removal (0-for-1) manipulation, respectively. Since each LUT can realize an arbitrary internal function with respect to a specified number of input variables, there is no sufficient condition at the logic design level for simple wire addition. Moreover, in general, simple addition of a wire has no effects for removal of another wire, and it is important to derive the condition for non-simple and effective wire addition. We found the SPFD-based condition that wire addition is likely to make another wire redundant or replaceable, and developed an optimization procedure utilizing this effective wire addition. According to the experimental results, when we focused on the delay reduction of LUT-based FPGA circuits, our method reduced the delay by 24.2% from the initial circuits, while the conventional SPFD-based logic optimization and the enhanced global rewiring reduced it by 14.2% and 18.0%, respectively. Thus, our method presented in this paper is sufficiently practical, and is expected to improve the circuit performance.