ESD protection design with lateral DMOS transistor in 40-V BCD technology
ESD protection design with lateral DMOS transistor in 40-V BCD technology
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DOI：
10.1109/ted.2010.2079530
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发表时间：
2010-07
期刊：
影响因子：
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通讯作者：
Chang-Tzu Wang;M. Ker;Tien-Hao Tang;K. Su
中科院分区：
文献类型：
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作者：
Chang-Tzu Wang;M. Ker;Tien-Hao Tang;K. Su
提出了一种适用于智能功率应用的横向双扩散MOS（LDMOS）晶体管ESD保护设计。利用所提出的ESD检测电路，n沟道LDMOS可以在ESD应力期间快速导通以保护输出驱动器。所提出的ESD保护电路已在0.35 µm 5 V/40 V双极CMOS DMOS（BCD）工艺中成功验证。此外，电源轨ESD保护设计也可以通过堆叠结构来实现，以保护40 V电源引脚，而不会在智能功率IC中出现闩锁问题。
ESD protection designs for smart power applications with lateral double-diffused MOS (LDMOS) transistor were proposed. With the proposed ESD detection circuits, the n-channel LDMOS can be quickly turned on to protect the output drivers during ESD stress. The proposed ESD protection circuits have been successfully verified in a 0.35-µm 5-V/40-V bipolar CMOS DMOS (BCD) process. In addition, the power-rail ESD protection design can be also achieved with stacked structure to protect 40-V power pins without latchup issue in the smart power ICs.