A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems

A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems
复制标题

DOI:
10.1007/s00422-011-0435-9
复制
发表时间:
2011-05-01
影响因子:
1.9
通讯作者:
Meier, Karlheinz
Meier, Karlheinz
中科院分区:
工程技术3区
文献类型:
--
作者:
Bruederle, Daniel;Petrovici, Mihai A.;Meier, Karlheinz

文献摘要

被引文献

相似文献

在本文中,我们提出了一个方法框架,以满足即将到来的加速和高度可配置的神经形态硬件系统的新需求。我们详细描述了目前正在开发的具有4500万个可编程和动态突触的设备,并概述了将该平台投入运行所产生的概念挑战。更具体地说,我们的目标是建立这个神经形态系统作为一个灵活的和神经科学上有价值的建模工具,可以被非硬件专家使用。我们认为各个功能方面对于实现这一目的至关重要,并且我们引入了一个一致的工作流,其中详细描述了实现建议步骤的所有相关模块:将硬件接口集成到独立于模拟器的模型描述语言PyNN中;PyNN域和适当硬件配置之间的全自动转换;未来神经形态系统的可执行规范,可以无缝集成到这个生物到硬件映射过程中,作为所有软件层和可能的硬件设计修改的测试平台;评估方案从专用基准库部署模型,将虚拟或原型硬件设备生成的结果与参考软件模拟进行比较,并分析差异。将这些组件集成到一个硬件-软件工作流中,为正在进行的准备研究提供了一个生态系统,支持硬件设计过程,并代表了模型到硬件映射软件成熟的基础。各种实验结果证明了后者的功能性和灵活性。
In this article, we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results.