Decentralized equalization for massive MU-MIMO on FPGA
Decentralized equalization for massive MU-MIMO on FPGA
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DOI：
10.1109/acssc.2017.8335613
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发表时间：
2017-10
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通讯作者：
Kaipeng Li;Charles Jeon;Joseph R. Cavallaro;Christoph Studer
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文献类型：
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作者：
Kaipeng Li;Charles Jeon;Joseph R. Cavallaro;Christoph Studer
大规模多用户多输入多输出(MU-MIMO)技术依赖于在同一时频资源中为数十个用户设备提供服务的大型天线阵。基站(BS)存在数百个天线单元和射频(RF)链，通过细粒度波束形成实现了高频谱效率，但也带来了重大的实际实施挑战。具体地，在大规模MU-MIMO上行链路(用户向BS发送)中使用的传统线性均衡算法(例如迫零)通常需要集中式架构，这导致基带处理单元和RF链之间的计算复杂性和互连带宽过高。为了缓解复杂度和带宽瓶颈，我们提出了一种分布式前馈结构的VLSI设计和基于大MIMO近似消息传递(LAMA)的并行均衡算法。我们使用高级综合(HLS)来开发VLSI架构，并给出了相应的FPGA实现结果。结果表明，提出的分散式LAMA均衡器的性能和复杂度与现有的寄存器传送级集中式均衡器的性能相当。
Massive multi-user multiple-input multiple-output (MU-MIMO) relies on large antenna arrays that serve tens of user equipments in the same time-frequency resource. The presence of hundreds of antenna elements and radio-frequency (RF) chains at the base station (BS) enables high spectral efficiency via fine-grained beamforming, but poses significant practical implementation challenges. In particular, conventional linear equalization algorithms used in the massive MU-MIMO uplink (users transmit to the BS), such as zero-forcing, typically require centralized architectures, which cause excessively high computational complexity and interconnect bandwidth between the baseband processing unit and the RF chains. In order to mitigate the complexity and bandwidth bottlenecks, we propose a VLSI design of a decentralized feed-forward architecture and a parallel equalization algorithm relying on large-MIMO approximate message passing (LAMA). We use high-level synthesis (HLS) to develop the VLSI architecture and provide corresponding FPGA implementation results. Our results demonstrate that the proposed decentralized LAMA equalizer achieves competitive performance and complexity as existing centralized solutions that have been designed on register-transfer level.