Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
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线程重定位：一种容忍芯片多处理器中硬错误的运行时架构
DOI：
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发表时间：
2010
影响因子：
3.7
通讯作者：
S. Kundu
中科院分区：
文献类型：
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作者：
O. Khan;S. Kundu
随着半导体行业继续不懈地推动纳米 CMOS 技术，器件可靠性和硬错误的发生已成为多核中的主要问题。尽管使用纠错码或备用行和列来保护常规内存结构免受硬错误的影响，但核心内的许多结构并未受到保护。即使先验地知道硬错误的位置，禁用有故障的核心也会导致严重的性能损失。几种提出的技术使用微架构冗余来允许有缺陷的核心继续运行。这些技术很有吸引力，但由于额外冗余的成本增加而受到限制，这对无错误核心没有任何好处，或者由于微架构提供的自然冗余而覆盖范围有限。我们建议利用芯片多处理器中的核间冗余来实现硬错误容错。我们的方案结合了硬件重新配置以确保减少内核的功能，以及软件运行时层（微管理程序）来管理线程到内核的映射。 Microvisor 观察线程不断变化的阶段行为，并启动线程重新定位，以使线程的计算需求与内核的功能相匹配。我们的结果表明，在存在性能下降的核心的情况下，微管理程序可将性能损失平均减轻百分之二。
As the semiconductor industry continues its relentless push for nano-CMOS technologies, device reliability and occurrence of hard errors have emerged as a dominant concern in multicores. Although regular memory structures are protected against hard errors using error correcting codes or spare rows and columns, many of the structures within the cores are left unprotected. Even if the location of hard errors is known a priori, disabling faulty cores results in a substantial performance loss. Several proposed techniques use microarchitectural redundancy to allow defective cores to continue operation. These techniques are attractive, but limited due to either added cost of additional redundancy that offers no benefits to an error-free core, or limited coverage, due to the natural redundancy offered by the microarchitecture. We propose to exploit the intercore redundancy in chip multiprocessors for hard-error tolerance. Our scheme combines hardware reconfiguration to ensure reduced functionality of cores, and a runtime layer of software (microvisor) to manage mapping of threads to cores. Microvisor observes the changing phase behavior of threads and initiates thread relocation to match the computational demands of threads to the capabilities of cores. Our results show that in the presence of degraded cores, microvisor mitigates performance losses by an average of two percent.