Sub-clock power-gating technique for minimising leakage power during active mode
Sub-clock power-gating technique for minimising leakage power during active mode
复制标题
副时钟功率门控技术可最大限度地减少活动模式期间的泄漏功率
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
Stephen Hill
中科院分区：
文献类型：
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作者：
Jatin N. Mistry;B. Al;D. Flynn;Stephen Hill
本文提出了一种降低数字电路泄漏功率的新技术——分时钟功率门控技术。所提出的技术与电压和频率缩放同时工作，并且在活动模式期间通过时钟周期内的功率门控实现功率降低，而传统的功率门控在空闲模式期间应用。所提出的技术可以使用标准EDA工具实现，只需对标准功率门控设计流程进行简单修改。使用90nm技术库，该技术通过两个案例研究进行验证：16位并行乘法器和ARM Cortex-M0™微处理器，由我们的工业项目合作伙伴提供。与没有子时钟功率门控的设计相比，在给定的功率预算下，我们发现在乘法器和微处理器的情况下，节省的泄漏功率分别使能效提高了45倍和2.5倍。
This paper presents a new technique, called sub-clock power gating, for reducing leakage power in digital circuits. The proposed technique works concurrently with voltage and frequency scaling and power reduction is achieved by power gating within the clock cycle during active mode unlike traditional power gating which is applied during idle mode. The proposed technique can be implemented using standard EDA tools with simple modifications to the standard power gating design flow. Using a 90nm technology library, the technique is validated using two case studies: 16-bit parallel multiplier and ARM Cortex-M0™ microprocessor, provided by our industrial project partner. Compared to designs without sub-clock power gating, in a given power budget, we show that leakage power saved allows 45× and 2.5× improvements in energy efficiency in the case of multiplier and microprocessor, respectively.