A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter
A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter
复制标题
70MS/s 110mW 8b CMOS 折叠和插值 A/D 转换器
DOI：
10.1109/4.482155
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发表时间：
1995
期刊：
影响因子：
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通讯作者：
Ardie G. Venes
中科院分区：
文献类型：
--
作者：
B. Nauta;Ardie G. Venes
提出了一种基于折叠内插技术的CMOS模/数转换器。该技术已成功应用于双极型A/D转换器中，目前也可应用于CMOS型工艺中。通过在折叠放大器的输出端使用跨阻放大器来增加A/D转换器的模拟带宽，并且由于精心的电路设计，比较器不需要偏移补偿。结果得到了一个面积小(0.7 mm/sup 2/in 0.8/spl Mu/m CMOS)、高速(70 MS/S)、低功耗(5V电源下110 mW，含参考梯形图)的A/D转换器。该电路的3.3V电源版本以45 MS/S的速度运行，功耗为45 mW。
A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm/sup 2/ in 0.8 /spl mu/m CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.