On tests to detect via opens in digital CMOS circuits
On tests to detect via opens in digital CMOS circuits
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数字 CMOS 电路中过孔开路检测的测试
DOI：
10.1145/1391469.1391682
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
Chen Liu
中科院分区：
文献类型：
--
作者：
S. Reddy;I. Pomeranz;Chen Liu
我们考虑基于电压（逻辑）测试以检测数字CMOS电路的完整打开。已知开放缺陷在当前的VLSI技术中很普遍，而VIA已知是互连打开的主要部位。由于打开的通过而导致的电路节点上的电压由多个电路参数确定。随着VLSI电路的特征大小减小，对于电路参数值的精确知识可能很难（即使不是不可能）获得。因此，开发方法生成测试以检测不需要准确了解电路参数的方法很重要。我们提出了新的测试类别，以通过基于电压（逻辑）测试开启，即使对电路参数的了解不精确也是有效的。提出的检测开放式通过的测试构成是一对受开放缺陷影响的电路节点的约束cat-at故障测试。一类提出的测试称为电路参数独立测试，即使完全缺乏对电路参数的了解，也可以通过打开。实验结果表明，可以使用拟议的约束测试获得开放式vias的高覆盖率。
We consider voltage based (logic) tests to detect complete opens in digital CMOS circuits. Open defects are known to be prevalent in the current VLSI technologies and vias are known to be the primary sites of interconnect opens. The voltage on a circuit node that is disconnected due to an open via is determined by several circuit parameters. As the feature size of VLSI circuits decreases, precise knowledge of the values of circuit parameters may be difficult, if not impossible, to obtain. Thus, it is important to develop methods to generate tests to detect opens that do not require accurate knowledge of circuit parameters. We propose new classes of tests to detect via opens with voltage based (logic) tests that are effective even with imprecise knowledge of circuit parameters. The proposed tests to detect an open via are constituted as a pair of constrained stuck-at fault tests for the circuit node affected by the open defect. One class of proposed tests called circuit parameter independent tests detect via opens even in the case of complete lack of knowledge of the circuit parameters. Experimental results demonstrate that high coverage of open vias can be obtained using the proposed constrained tests.