Architectural-space exploration of approximate multipliers
Architectural-space exploration of approximate multipliers
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DOI：
10.1145/2966986.2967005
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发表时间：
2016-11
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通讯作者：
Semeen Rehman;Walaa El-Harouni;M. Shafique;Akash Kumar;J. Henkel
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作者：
Semeen Rehman;Walaa El-Harouni;M. Shafique;Akash Kumar;J. Henkel
本文提出了一种设计近似乘法器的建筑空间探索方法。与最先进的方法不同，我们的方法通过适应三个关键参数来生成各种设计点：(1)不同类型的初等近似乘法模块，(2)不同类型的用于求和部分乘积的初等加法器模块，以及(3)宽位乘法器设计中用于近似的位选择。生成和探索这样的设计空间可以实现具有不同近似级别的大范围乘法器，每个乘法器显示不同的面积、功率和输出质量，从而促进更高抽象级别的近似计算。我们使用Synopsys Design Compiler和TSMC 45nm技术库合成了我们的设计，并使用ModelSim门级仿真进行了验证。各种设计的功率和质量评估分别使用PrimeTime和行为模型进行。然后将选定的设计部署到JPEG应用程序中。为了再现性和促进更高抽象层的进一步研究和开发，我们已经将这些近似乘数器和加法器的RTL和行为模型作为开源库发布在https://sourceforge.net/projects/lpaclib/上。
This paper presents an architectural-space exploration methodology for designing approximate multipliers. Unlike state-of-the-art, our methodology generates various design points by adapting three key parameters: (1) different types of elementary approximate multiply modules, (2) different types of elementary adder modules for summing the partial products, and (3) selection of bits for approximation in a wide-bit multiplier design. Generation and exploration of such a design space enables a wide-range of multipliers with varying approximation levels, each exhibiting distinct area, power, and output quality, and thereby facilitates approximate computing at higher abstraction levels. We synthesized our designs using Synopsys Design Compiler with a TSMC 45nm technology library and verified using ModelSim gate-level simulations. Power and quality evaluations for various designs are performed using PrimeTime and behavioral models, respectively. The selected designs are then deployed in a JPEG application. For reproducibility and to facilitate further research and development at higher abstraction layers, we have released the RTL and behavioral models of these approximate multipliers and adders as an open-source library at https://sourceforge.net/projects/lpaclib/.