Tolerating hard faults in microprocessor array structures
Tolerating hard faults in microprocessor array structures
复制标题
容忍微处理器阵列结构中的硬故障
DOI：
--
复制
发表时间：
2004
期刊：
影响因子：
--
通讯作者：
Daniel J. Sorin
中科院分区：
文献类型：
--
作者：
Fred A. Bower;Paul G. Shealy;S. Ozev;Daniel J. Sorin
在本文中，我们提出了一种硬件技术，称为自修复阵列结构（SRAS），用于屏蔽硬故障的微处理器阵列结构，如重排序缓冲区和分支历史表。SRAS掩盖了可能导致系统恢复缓慢的错误。为了检测行错误，对行的每次写入都被镜像到专用的“检查行”。然后，我们读出写入行和检查行，并比较它们的结果。为了纠正错误，SRAS用间接级别映射出错误的数组行。
In this paper, we present a hardware technique, called self-repairing array structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history table. SRAS masks errors that could otherwise lead to slow system recoveries. To detect row errors, every write to a row is mirrored to a dedicated "check row". We then read out both the written row and check row and compare their results. To correct errors, SRAS maps out faulty array rows with a level of indirection.