NMOS drive current reduction caused by transistor layout and trench isolation induced stress
NMOS drive current reduction caused by transistor layout and trench isolation induced stress
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晶体管布局和沟槽隔离引起的应力导致 NMOS 驱动电流降低
DOI：
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发表时间：
1999
期刊：
影响因子：
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通讯作者：
M. Manley
中科院分区：
文献类型：
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作者：
G. Scott;J. Lutze;M. Rubin;F. Nouri;M. Manley
本文描述了一个以前从未报道过的现象，其中相同的栅极长度的NMOS晶体管表现出显着的布局敏感性。驱动电流可以减少高达13%，这取决于栅极的扩散重叠。由来自沟槽隔离边缘的应力引起的迁移率降低是性能下降的根本原因。PMOS器件不受影响。模拟结果表明，应力变化强烈的距离，从沟槽边缘，并与整体扩散的大小。应力也是窄宽度效应的主要组成部分，并解释了NMOS和PMOS器件的Idsat随W缩放不同的原因。
This paper describes a previously unreported phenomenon wherein NMOS transistors of identical gate length exhibit a significant sensitivity to layout. Drive current may be reduced up to 13%, depending on diffusion overlap of gate. Mobility reduction, induced by stress from the trench isolation edge, is the root cause of the performance degradation. PMOS devices are not affected. Simulation results show that stress varies strongly with distance from the trench edge, and with overall diffusion size. Stress is also a major component of narrow-width effects, and explains why Idsat scaling with W differs for NMOS and PMOS devices.