The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUs
The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUs
复制标题
节能型 GPGPU 的 NoC 端内存访问调度设计
DOI：
10.1007/s10766-017-0521-2
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发表时间：
2018
影响因子：
1.5
通讯作者：
Wang Zhiying
中科院分区：
文献类型：
--
作者：
Liu Wenjie;Ma Sheng;Huang Libo;Wang Zhiying
内存访问调度方案通常在内存控制器中执行，对于减轻gpgpu的内存系统负担有显著的影响。现有的乱序调度方案，如FR-FCFS，通过在目的地重新排序内存请求序列来提高内存访问效率。然而，它们的有效性是以复杂的逻辑和高功耗为代价的。本文基于片上网络的传输是破坏行访问局部性和导致存储器访问效率低下的主要因素这一关键观点，提出了一种noc端存储器访问调度方法。通过适当的noc端优化，可以在内存控制器中使用直接的顺序调度，以简化调度逻辑并缓解紧张的功率包络。此外，我们还引入了一些轻量级优化来进一步提高系统性能。在内存密集型应用上的实验结果表明，与FR-FCFS相比，我们提出的方案整体性能提高10.5%，功耗降低20%，能效提高36.9%。
Memory access scheduling schemes, often performed in memory controllers, have a marked impact on alleviating the heavy burden placed on memory systems of GPGPUs. Existing out-of-order scheduling schemes, like FR-FCFS, improve memory access efficiency by reordering memory request sequences at the destination. Their effectiveness, however, is at the expense of complex logics and high power consumption. In this paper, we propose a NoC-side memory access scheduling based on the key insight that the transmission of on-chip networks is the dominating factor in destroying the row access locality and causing poor memory access efficiency. With appropriate NoC-side optimization, the straight-forward in-order scheduling can be used in memory controllers to simplify scheduling logics and alleviate the tight power envelope. Moreover, we introduce several light-weight optimizations to further improve the system performance. Experimental results on memory-intensive applications show that, comparing with FR-FCFS, our proposed scheme increases the overall system performance by 10.5%, reduces the power consumption by 20% and improves the energy efficiency by 36.9%.