A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA
A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA
复制标题
在低端 SRAM FPGA 中实现的混合容错 LEON3 软核处理器
DOI：
10.1109/tns.2016.2636574
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发表时间：
2017
影响因子：
1.8
通讯作者：
Luis Parra
中科院分区：
文献类型：
--
作者：
A. Lindoso;L. Entrena;M. García;Luis Parra
在这项工作中，我们在低端的现场可编程门阵列(ARTX-7)上实现了一个混合容错的LEON3软核处理器，并以增量的方式评估了它在中子辐照和故障注入下的错误检测能力。错误缓解方法结合使用存储器的SEC/DED代码、检测控制流错误的硬件监视器、检测数据错误的基于软件的技术以及配置存储器清理和修复，以避免错误累积。该方案能显著提高容错性，可以完全嵌入到低端的现场可编程门阵列中，具有较低的开销和较低的侵入性。
In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and fault injection in an incremental manner. The error mitigation approach combines the use of SEC/DED codes for memories, a hardware monitor to detect control-flow errors, software-based techniques to detect data errors and configuration memory scrubbing with repair to avoid error accumulation. The proposed solution can significantly improve fault tolerance and can be fully embedded in a low-end FPGA, with reduced overhead and low intrusiveness.