Sub-50-nm $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ MOSFETs With Various Barrier Layer Materials
Sub-50-nm $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ MOSFETs With Various Barrier Layer Materials
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DOI：
10.1109/led.2011.2172910
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发表时间：
2012
影响因子：
4.9
通讯作者：
F. Xue;A. Jiang;Han Zhao;Yen‐Ting Chen;Yanzhan Wang;F. Zhou;J. Lee
中科院分区：
文献类型：
--
作者：
F. Xue;A. Jiang;Han Zhao;Yen‐Ting Chen;Yanzhan Wang;F. Zhou;J. Lee
亚50纳米In0.7Ga0.3As MOSFET的高k介质Al 2 O3已被证明和研究。研究了具有不同势垒层材料（即，InP和InAlAs）的器件进行了分析和比较，没有一个势垒层。具有InP/InAlAs阻挡层的40 nm栅长In0.7Ga0.3 As MOSFET表现出130 mV/dec的亚阈值摆幅、174 mV/V的漏致阻挡层降低以及Vds = 1 V时570 mS/mm的非本征跨导。还分析了有和没有阻挡层材料的埋沟道In0.7Ga0.3As MOSFET的缩放行为。
Sub-50-nm In0.7Ga0.3As MOSFETs with high-k dielectric Al2O3 have been demonstrated and investigated. The device performance of buried-channel In0.7Ga0.3As MOSFETs with various barrier layer materials (i.e., InP and InAlAs) has been analyzed and compared to that of devices without a barrier layer. The 40-nm-gate-length In0.7Ga0.3 As MOSFETs with InP/InAlAs barrier exhibit a subthreshold swing of 130 mV/dec, a drain-induced barrier lowering of 174 mV/V, and an extrinsic transconductance of 570 mS/mm at Vds = 1 V. Scaling behaviors of buried-channel In0.7Ga0.3As MOSFETs with and without a barrier layer material have also been analyzed.