Two phase clocked subthreshold adiabatic logic circuit
Two phase clocked subthreshold adiabatic logic circuit
复制标题
两相时钟亚阈值绝热逻辑电路
DOI：
10.1587/elex.12.20150695
复制
发表时间：
2015
影响因子：
0.8
通讯作者：
T. Sekine
中科院分区：
文献类型：
--
作者：
Kazunari Kato;Yasuhiro Takahashi;T. Sekine
能量收集是一种捕获有效电源的技术。然而，从环境中的电源获得的能量是不够的，因为只能从它产生低水平的电压/电流。因此，用于能量收集的逻辑电路的功耗必须降低。为了实现低功耗，我们可以考虑两种低功耗技术：绝热逻辑电路和亚阈值CMOS逻辑电路。本文提出了一种新的CMOS逻辑电路，它结合了绝热逻辑电路和亚阈值逻辑电路。所提出的电路采用具有不同幅度和频率的两相时钟电源电压。利用该方法设计并实现了与非、异或、半加器、全加器和4 × 4位乘法器电路。仿真和实测结果表明，与传统电路相比，该电路具有超低功耗特性。
Energy harvesting is a technique that captures an effective power source. However, the energy obtained from power resources in the environment is insufficient, as only low levels of voltage/current can be generated from it. Therefore, the power consumption of logic circuits for energy harvesting has to be reduced. To achieve low power consumption, we may consider two low-power techniques: the adiabatic logic circuit and the subthreshold CMOS logic circuit. In this paper, we propose a new CMOS logic circuit that combines the adiabatic logic circuit with the sub-threshold logic circuit. The proposed circuit employs two-phase clock supply voltages that have different amplitude and frequency. We design and implement NAND, XOR, half-adder, full-adder, and 4 × 4-bit multiplier circuits using the proposed method. The simulation and the measurement results show that the proposed circuit has an ultra-low-power characteristic compared with the conventional circuit.