A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
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DOI：
10.1109/jssc.2017.2782087
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发表时间：
2018-02-01
影响因子：
5.4
通讯作者：
Shanbhag, Naresh R.
中科院分区：
文献类型：
--
作者：
Kang, Mingu;Gonugondla, Sujan K.;Shanbhag, Naresh R.
提出了一种采用 65 nm CMOS 工艺的多功能内存推理处理器集成电路 (IC)。该原型采用深度内存架构 (DIMA)，通过每次预充电同时访问标准 6T 位单元阵列 (BCA) 的多行，并在 BCA 外围嵌入列间距匹配的低摆幅模拟处理，与传统数字架构相比，提高了能源效率和吞吐量。在此过程中，DIMA 利用机器学习 (ML) 算法的数据流与 SRAM 架构之间的协同作用来降低因数据移动而产生的主要能源成本。该原型 IC 集成了 16 kB SRAM 阵列，支持四种常用的 ML 算法：支持向量机、模板匹配、k 最近邻和匹配滤波器。硅测量结果表明，能源效率同时提高（点积模式）10 倍，吞吐量提高 5.3 倍，从而使能量延迟积减少 53 倍，并且可以忽略不计（
A multi-functional in-memory inference processor integrated circuit (IC) in a 65-nm CMOS process is presented. The prototype employs a deep in-memory architecture (DIMA), which enhances both energy efficiency and throughput over conventional digital architectures via simultaneous access of multiple rows of a standard 6T bitcell array (BCA) per precharge, and embedding column pitch-matched low-swing analog processing at the BCA periphery. In doing so, DIMA exploits the synergy between the dataflow of machine learning (ML) algorithms and the SRAMarchitecture to reduce the dominant energy cost due to data movement. The prototype IC incorporates a 16-kB SRAM array and supports four commonly used ML algorithms-the support vector machine, template matching, k-nearest neighbor, and the matched filter. Silicon measured results demonstrate simultaneous gains (dot product mode) in energy efficiency of 10x and in throughput of 5.3x leading to a 53x reduction in the energy-delay product with negligible (