Compact modeling of carbon nanotube transistor for early stage process-design exploration

Compact modeling of carbon nanotube transistor for early stage process-design exploration
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用于早期工艺设计探索的碳纳米管晶体管紧凑建模

DOI:
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发表时间:
2007
期刊:
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)
影响因子:
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通讯作者:
Yu Cao
Yu Cao
中科院分区:
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文献类型:
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作者:
A. Balijepalli;S. Sinha;Yu Cao

文献摘要

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碳纳米管晶体管(CNT)有望成为纳米级集成的首选技术。在这项工作中,我们开发了第一个紧凑的CNT模型,其目的是探索最佳的工艺和设计空间,为强大的低功耗应用。基于表面势的概念,新模型准确地预测了CNT器件在各种工艺和设计条件下的特性,如直径,手性,栅极介电常数和偏置电压。通过对接触的物理建模,该模型涵盖了肖特基势垒CNT(SB-CNT)和MOS型CNT。该模型不需要任何迭代,因此,显着提高了模拟效率,以支持大规模的设计研究。使用这个模型,我们基准的性能与CNT和22纳米CMOS工艺的FO 4逆变器。以下关键的见解是提取:(1)即使SB-CNT和现实的布局寄生效应,电路速度可以超过10倍的22纳米CMOS;(2)1- 1.5纳米的直径范围表现出最大的公差接触材料和工艺变化;(3)CNT电路允许更好地缩放电源电压(VDD),以降低功耗。对于固定的能耗和功耗,CNT的速度是22 nm CMOS的4倍。总的来说,新模型可以利用CNT进行高效的设计研究,为高速和低功耗应用提供了巨大的机会。
Carbon nanotube transistor (CNT) is promising to be the technology of choice for nanoscale integration. In this work, we develop the first compact model of CNT, with the objective to explore the optimal process and design space for robust low-power applications. Based on the concept of the surface potential, the new model accurately predicts the characteristics of a CNT device under various process and design conditions, such as diameter, chirality, gate dielectrics, and bias voltages. With the physical modeling of the contact, this model covers both the Schottky-barrier CNT (SB-CNT) and MOS-type CNT. The proposed model does not require any iteration and thus, significantly enhances the simulation efficiency to support large-scale design research. Using this model, we benchmark the performance of a FO4 inverter with CNT and 22nm CMOS technology. The following key insights are extracted: (1) even with the SB-CNT and realistic layout parasitics, the circuit speed can be more than 10X that of 22nm CMOS; (2) The diameter range of 1-1.5nm exhibits the maximum tolerance to contact materials and process variations; (3) a CNT circuit allows better scaling of the supply voltage (Vdd) for power reduction. For a fixed energy consumption and Vdd, the CNT speed is 4X that of 22nm CMOS. Overall, the new model enables efficient design research with CNT, revealing tremendous opportunities for both high-speed and low-power applications.