Sensor-wise methodology to face NBTI stress of NoC buffers
Sensor-wise methodology to face NBTI stress of NoC buffers
复制标题
应对 NoC 缓冲区 NBTI 压力的传感器方式方法
DOI：
10.7873/date.2013.216
复制
发表时间：
2013
期刊：
影响因子：
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通讯作者：
W. Fornaciari
中科院分区：
文献类型：
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作者：
Davide Zoni;W. Fornaciari
从性能和可靠性的角度来看，片上网络（NoC）是新的众核架构的关键组成部分。不幸的是，CMOS技术的不断扩展引起了对NBTI和应力迁移等失效机制的严重关注。工艺变化使得这种情况更加困难，降低了芯片制造期间的器件寿命和性能可预测性。本文提出了一种新的合作传感器明智的方法，以减少NBTI退化的片上网络（NoC）虚拟通道（VC）缓冲区，考虑工艺变化的影响。引入到参考NoC模型的变化显示出低于4%的面积开销。实验验证得到使用周期精确的模拟器，考虑到真实的和合成的交通模式。我们将我们的方法与用作参考模型的最佳无传感器轮询方法进行比较。建议的传感器明智的策略实现了高达26.6%和18.9%的活动因子的改善，分别在合成和真实的交通模式的参考政策。此外，相对于不考虑NBTI的基线NoC，显示了高达54.2%的净NBTI Vth节省。
Networks-on-Chip (NoCs) are a key component for the new many-core architectures, from the performance and reliability stand-points. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms such as NBTI and stress-migration. Process variation makes harder the scenario, decreasing device lifetime and performance predictability during chip fabrication. This paper presents a novel cooperative sensor-wise methodology to reduce the NBTI degradation in the network on-chip (NoC) virtual channel (VC) buffers, considering process variation effects as well. The changes introduced to the reference NoC model exhibit an area overhead below 4%. Experimental validation is obtained using a cycle accurate simulator considering both real and synthetic traffic patterns. We compare our methodology to the best sensor-less round-robin approach used as reference model. The proposed sensor-wise strategy achieves up to 26.6% and 18.9% activity factor improvement over the reference policy on synthetic and real traffic patterns respectively. Moreover a net NBTI Vth saving up to 54.2% is shown against the baseline NoC that does not account for NBTI.