A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine
A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine
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DOI：
10.1109/isscc.2013.6487709
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发表时间：
2013-03
期刊：
影响因子：
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通讯作者：
Kin-Chu Ho;Po-Chao Fang;Hsiang-Pang Li;Cheng-Yuan Michael Wang;Hsie-Chia Chang
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文献类型：
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作者：
Kin-Chu Ho;Po-Chao Fang;Hsiang-Pang Li;Cheng-Yuan Michael Wang;Hsie-Chia Chang
为了满足更高存储密度的要求，每单元存储多比特技术被广泛采用。如文献[1]所示，通过使用错误检测(ED)方案的4b/单元闪存在存储单元的两侧分别存储2b数据。由于噪声容限变小，如果不相应地调整感测电平(电压)，则由于编程干扰、数据保留和温度变化引起的分布漂移将导致更高的原始误比特率(RBER)。ED方案可以通过计数和存储阈值电压(VTH)低于第i个感测电平(Vref I)的单元数量(Ni)来检测漂移方向。图12.7.1展示了一个页面大小为1KB的简单示例。在读操作期间，对其VTH低于Vref i的单元的数量(Ni，测量的)进行计数并与Ni进行比较。当Ni、被测量和Ni足够接近时，ED方案可以找到次优的传感电平。本文介绍了一种基于ONO的16 GB 45nm4b/cell的电荷捕获(CT)闪存，其容量可达6b/cell。由于6b/cell的相邻分布彼此更接近，即使采用ED方案的BCH码也不能纠正所有的图案。然而，通过使用新的1-3-3映射和LDPC码以及开发的漂移免疫软测量(DI-SS)引擎，45 nm 4b/cell CT闪存的速度提高到了6b/cell。编程数据的数据流也如图12.7.1所示。
To satisfy the demand of higher storage density, storing multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becomes smaller, the distribution drifts due to program disturb, data retention and temperature variation will cause higher raw bit-error-rate (RBER) if the sensing level (voltage) are not adjusted accordingly. The ED scheme can detect the drift direction by counting and storing the number of cells (Ni) with threshold voltage (VTH) below the ith sensing level (VREF i). A simple example with page size 1KB is demonstrated in Fig. 12.7.1. During a read operation, the number of cells (Ni, measured) whose VTH below VREF i is counted and compared to Ni. The ED scheme can find out a sub-optimal sensing level when Ni, measured and Ni is close enough. In this paper, a production 16Gb 45nm 4b/cell ONO-based charge-trapping (CT) Flash memory is demonstrated to achieve 6b/cell capability. Since the adjacent distributions for 6b/cell are much closer to each other, even a BCH code with ED scheme fails to correct all the patterns. However, by using a new 1-3-3 mapping and LDPC codes with a developed drift-immune soft-sensing (DI-SS) engine, the 45nm 4b/cell CT Flash memory is boosted to 6b/cell. The data flow of programming data is also shown in Fig. 12.7.1.