Investigating Transactional Memory for High Performance Embedded Systems
Investigating Transactional Memory for High Performance Embedded Systems
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DOI:
10.1007/978-3-030-52794-5_8
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发表时间:
2020-06-12
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影响因子:
--
通讯作者:
Ungerer T
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文献类型:
--
作者:
Piatka C;Amslinger R;Haas F;Weis S;Altmeyer S;Ungerer T
We present a Transaction Management Unit (TMU) for Hardware Transactional Memories (HTMs). Our TMU enables three different contention management strategies, which can be applied according to the workload. Additionally, the TMU enables unbounded transactions in terms of size. Our approach tackles two challenges of traditional HTMs: (1) potentially high abort rates, (2) missing support for unbounded transactions. By enhancing a simulator with a transactional memory and our TMU, we demonstrate that our TMU achieves speedups of up to 4.2 and reduces abort rates by a factor of up to 11.6 for some of the STAMP benchmarks.
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影响因子:
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作者:
Chuang, Weihaw;Narayanasamy, Satish;Calder, Brad
通讯作者:
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影响因子:
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作者:
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DOI:
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发表时间:
2005-01-01
期刊:
DISTRIBUTED COMPUTING, PROCEEDINGS
影响因子:
--
作者:
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通讯作者:
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