Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
复制标题
同步 CMOS 数字电路中的时钟树优化，利用电源电流瞬态折叠来降低衬底噪声
DOI：
10.1109/dac.2002.1012658
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
G. Gielen
中科院分区：
文献类型：
--
作者：
M. Badaroglu;K. Tiri;S. Donnay;P. Wambacq;H. Man;I. Verbauwhede;G. Gielen
在具有零延迟的同步时钟分配网络中，数字电路在时钟边沿上同时切换，因此它们由于电源电流的尖峰而产生衬底噪声。我们提出了一种新的方法，优化时钟树，减少基板代通过使用统计单周期电源电流分布计算每个时钟区域考虑到时序约束。我们的方法是新颖的，因为它使用了一个错误驱动的压缩数据集在优化过程中指定的基板噪声显着降低的时钟区域的数量。它还产生作为时钟偏斜的函数的计算延迟的质量分析。实验结果表明，具有四个时钟区的电路的衬底噪声产生的减少>/spl倍/2，其中的时钟区被优化。
In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the clock tree for less substrate generation by using statistical single cycle supply current profiles computed for every clock region taking the timing constraints into account. Our methodology is novel as it uses an error-driven compressed data set during the optimization over a number of clock regions specified for a significant reduction in substrate noise. It also produces a quality analysis of the computed latencies as a function of the clock skew. The experimental results show >/spl times/2 reduction of substrate noise generation from the circuits having four clock regions of which the latencies are optimized.