Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget
Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget
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瞬态故障的错误屏蔽：基于用户指定功率和延迟预算的容错数据路径探索
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发表时间：
2014
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通讯作者：
Saumya Bhadauria
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作者：
A. Sengupta;Saumya Bhadauria
本文提出了一种新的探索过程中的最佳容错数据路径的基础上，用户指定的功率和延迟预算在高层次综合（HLS），能够掩盖错误发生通过单周期和多周期的瞬态故障。探索框架是通过生物模拟E。大肠杆菌生命周期。这一方法的主要创新之处如下：a）新颖的多周期容错算法，B）新颖的设计空间探索（DSE）方法，其将所提出的容错算法沿着与用户指定的冲突功率延迟约束相结合，所述冲突功率延迟约束引导该棘手的搜索问题达到最优解，c）新型双模冗余（DMR）一种具有等效电路方案的系统，该方案执行提取正确输出的等效功能，如传统上使用三重模概念所做的那样冗余（TMR）和表决器。结果表明，与最近的类似方法相比，结果质量（QoR）平均提高>24%，硬件使用减少> 57%。
This paper presents a novel exploration process of an optimal fault tolerant data path based on user specified power and delay budget during high level synthesis (HLS) that is capable of masking error occurred through single and multi cycle transient faults. The exploration framework is driven through bio-mimicking of E. Coli bacterium lifecycle. The major novelties of this approach are as follows: a) novel multi-cycle fault tolerant algorithm, b) novel design space exploration (DSE) approach that combines proposed fault tolerant algorithm along with user specified conflicting power-delay constraint that guides this intractable search problem to reach an optimal solution, c) novel double modular redundant (DMR) system with equivalent circuit scheme that performs the equivalent function of extracting the correct output as conventionally done using the concept of triple modular redundant (TMR) and voter. Results indicated an average improvement in quality of results (QoR) of >24% and reduction in hardware usage of > 57 % were obtained compared to a recent similar approach.