Verification of non-mainline functions in todays processor chips
Verification of non-mainline functions in todays processor chips
复制标题
当今处理器芯片中非主线功能的验证
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
A. Goryachev
中科院分区：
文献类型：
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作者：
J. Koesters;A. Goryachev
在现代芯片开发周期中，与传统的功能验证任务相比，非主线/非功能验证越来越重要，并且占总验证工作的三分之一。非主线逻辑的目的是操作、维护和调试芯片。因此，芯片的不断增加的复杂性直接影响非主线逻辑的复杂性，并因此影响其验证。此外，非主线世界不再是纯粹的硬件，而是软件和硬件的复杂混合体。我们认为，传统的约束随机验证方法不适用于非主线领域，验证应该基于使用场景。此外，这些场景必须正式指定，以避免歧义，并允许参与芯片开发的不同团队进行协作。
In a modern chip development cycle non-mainline / non-functional verification is gaining importance compared to traditional functional verification tasks and takes up to one third of the total verification effort. The purpose of non-mainline logic is to operate, maintain, and debug the chip. Ever-increasing complexity of the chip, thus, directly affects the complexity of the non-mainline logic and as a result, the verification thereof. Moreover, the non-mainline world is no longer pure hardware, but an intricate mix of software and hardware. We claim that traditional constrained-random verification methods are not valid for the non-mainline domain and the verification should be based on usage scenarios. Moreover, these scenarios must be formally specified to avoid ambiguity and allow collaboration of different teams involved in the chip development.