A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash
A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash
复制标题
NAND Flash低位宽LDPC最小和译码方案
DOI：
10.1109/tcad.2021.3100273
复制
发表时间：
2021
影响因子：
2.9
通讯作者：
Changsheng Xie
中科院分区：
文献类型：
--
作者：
Lanlan Cui;Xiaojian Liu;Fei Wu;Zhonghai Lu;Changsheng Xie
对于NAND闪存，设计一个好的低密度奇偶校验（LDPC）译码算法可以保证数据的可靠性。当解码算法在硬件中实现时，有必要在实现复杂度和解码性能之间实现有吸引力的折衷。本文提出了一种新的低位宽解码方案。该方案采用准循环LDPC码（QC-LDPC），并通过限制每次校验节点（CN）更新时最小值和次小值的幅度，改进了行分层的归一化最小和算法。仿真结果表明，我们的方法实现了较低的不可纠正的比特错误率（UBER）的计算复杂度可以忽略不计的增加，特别是与低精度的输入对数似然比（LLR）。
For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve an attractive tradeoff between implementation complexity and decoding performance. In this article, a novel low-bit-width decoding scheme is introduced. In this scheme, the quasi-cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower uncorrectable bit error rate (UBER) with a negligible increase in computational complexity, especially with low-precision input log-likelihood ratio (LLR).