Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing
Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing
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DOI：
10.1109/tcsii.2012.2195058
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发表时间：
2012-05
期刊：
影响因子：
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通讯作者：
Kai He;Jin Sha;Zhongfeng Wang
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文献类型：
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作者：
Kai He;Jin Sha;Zhongfeng Wang
多进制低密度奇偶校验码(NB-LDPC)是二进制LDPC码的扩展，具有明显更好的性能。尽管已经提出了各种低复杂度的迭代译码算法，但由于其高复杂度和长延迟，NB-LDPC译码的VLSI实现仍然是一个巨大的挑战。本文针对Min-Max译码算法，提出了一种高效的校验节点处理方案，大大降低了处理时延。此后，可以设计出高效的校验节点单元(CNU)。与前人的工作相比，CNU的延迟可以降低到52%以下。此外，还设计了(620,310)NB-LDPC码的译码器，以验证所提出的技术的有效性。
Nonbinary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity iterative decoding algorithms have been proposed, the VLSI implementation of NB-LDPC decoders still remains a big challenge due to its high complexity and long latency. In this brief, a highly efficient check node processing scheme, which the processing delay greatly reduced, is proposed for Min-max decoding algorithm. Thereafter, an efficient check node unit (CNU) can be designed. Compared with previous works, the latency of the CNU could be reduced to less than 52%. In addition, a decoder for a (620, 310) NB-LDPC code is designed to demonstrate the efficiency of the presented techniques.