Analysis and demonstration of MEM-relay power gating
Analysis and demonstration of MEM-relay power gating
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MEM-继电器功率门控分析与演示
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
D. Markovic
中科院分区：
文献类型：
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作者：
H. Fariborzi;M. Spencer;V. Karkare;J. Jeon;R. Nathanael;Chengcheng Wang;Fred Chen;H. Kam;V. Pott;T. Liu;E. Alon;V. Stojanović;D. Markovic
本文指出，由于漏电极低，在某些应用中，使用功率门的芯片，即使使用当今相对较大的高压微电子机械(MEM)继电器，也可以获得比使用CMOS晶体管构建的芯片更低的总能量。简单的分析提供了作为技术参数函数的停机时间和节省估计的设计指南，并量化了规模化继电器设计的进一步好处。最后，我们演示了一个继电器芯片成功地给一个芯片上电，并给出了一个适用于自定时操作的继电器定时器。
This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with today's relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.