Design high bandwidth-density, low latency and energy efficient on-chip interconnect
Design high bandwidth-density, low latency and energy efficient on-chip interconnect
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DOI：
10.1109/islped.2017.8009171
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发表时间：
2017-07
期刊：
影响因子：
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通讯作者：
Yong Wang;Hui Wu
中科院分区：
文献类型：
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作者：
Yong Wang;Hui Wu
对于未来的高性能计算芯片，片上互连需要大带宽密度、低延迟和高能效，这对设计提出了重大挑战。提出了一种基于传输线的片上互连设计空间探索方法。首先，我们对片上传输线进行了优化，以最小化传输线的尺寸、信道损耗和码间干扰（ISI），从而最大化带宽密度。在此基础上，选择间距为55 μm的差分共面波导（CPW）作为传输线拓扑。接着，基于时域脉冲响应来表征从2至8 cm的信道长度的信道容量。各种均衡器进行了研究，这是用来增加ISI受限的信道容量。为了更好地利用大的均衡信道容量，采用脉冲幅度调制（PAM）代替传统的不归零（NRZ）信令。然后进行链路预算分析，以找到每个信道的最佳调制格式。为了验证我们的分析，几个收发器设计在28纳米CMOS技术。84 Gb/s PAM-8收发器在4 cm通道上实现1.5 Gb/s/μm带宽密度。无重复带宽密度为6.1 Gb/s/μm·cm，比之前的工作几乎大10倍。
For future high-performance computing chips, on-chip interconnect requires large bandwidth-density, low latency, and high energy-efficiency, which pose significant design challenges. This paper presents a design space exploration of transmission line based on-chip interconnect. First, we conduct an optimization of on-chip transmission lines to minimize the size, channel loss and inter-symbol-interference (ISI), hence to maximize the bandwidth-density. Based on the result, differential coplanar waveguide (CPW) with 55-µm pitch size is chosen as the transmission line topology. Next, channel capacities of channel lengths from 2 to 8 cm are characterized based on time-domain pulse responses. Various equalizers are studied, which are used to increase the ISI-limited channel capacity. To make better use of the large equalized channel capacity, pulse amplitude modulation (PAM) is employed instead of traditional non-return-to-zero (NRZ) signaling. A link budget analysis is then conducted to find the optimal modulation format for each channel. To verify our analyses, several transceivers are designed in 28-nm CMOS technology. An 84-Gb/s PAM-8 transceiver achieves 1.5-Gb/s/μm bandwidth-density over a 4-cm channel. The unrepeated bandwidth-density is 6.1 Gb/s/μm·cm, which is almost 10 times larger compared to prior work.