Enhanced bit-width optimization for linear circuits with feedbacks

Enhanced bit-width optimization for linear circuits with feedbacks
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带反馈的线性电路的增强位宽优化

DOI:
10.1109/idt.2014.7038607
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发表时间:
2014
期刊:
2014 9th International Design and Test Symposium (IDT)
影响因子:
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通讯作者:
Adel Belouchrani
Adel Belouchrani
中科院分区:
--
文献类型:
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作者:
El;Rima Bellal;S. Tagzout;H. Belbachir;Adel Belouchrani

文献摘要

被引文献

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位宽与精度的权衡需要复杂的方法开发和测试。本文提出了一种新的增量优化过程,与最近发布的结果相比,可以减少位宽。范围和精度的改进涉及所有数据路径互连。此外,甚至对于输入数据也提出了精度细化。提供了硬件实现的详细过程和结果,以显示与现有优化方法相比所取得的改进。为了说明并将我们的工作与现有结果进行比较,使用不同配置的 IIR 滤波器进行测试和实现。根据这些不同的配置,所提出的优化技术平均面积减少了 17% 到 30%。
Bit widths to accuracy trade offs require complex method development and testing. This paper presents a new process of incremental optimizations to get to reduced bit-widths compared to recently published results. Range and Precision improvements reach all the data path interconnections. More, a precision refinement is proposed even for input data. Detailed procedures and results of hardware implementations are provided to show the achieved improvements compared to existing optimization approaches. For illustration and to compare our work to existing results, different configurations of an IIR filter is used for tests and implementations. Depending on those different configurations, the proposed optimization techniques present an average of area reductions ranging from 17% to 30%.