Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs
Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs
复制标题
基于标准单元的可综合 FPGA 的物理设计注意事项
DOI：
10.1145/3337801.3337818
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
J. Anderson
中科院分区：
文献类型：
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作者：
Brett Grady;J. Anderson
由于其全定制设计方法和金属堆栈的使用，将现有的商用 FPGA 结构集成到片上系统 (SoC) 中具有挑战性。使用 ASIC 标准单元方法构建的可综合 FPGA 作为嵌入式 FPGA 结构的灵活替代方案已在工业界和学术界获得关注 [1-5]。这项工作涉及可综合 FPGA 的物理设计考虑因素，特别是 VTR 框架的目标对象 [1, 6]。我们解决以下问题：1）布局规划对合成结构的性能和延迟变化的影响； 2) 从标准单元布局中提取组件级延迟； 3) 检查片上延迟的空间相关性； 4) 将提取的布局后延迟注释到 VTR 的时序模型中。本文主要考虑以下问题：在完全综合的标准单元 FPGA 中，延迟的可预测性如何？因此，我们的工作有助于具有性能可预测性的高性能标准单元 FPGA 结构的实现和建模。
Integrating an existing commercial FPGA fabric into a system-on-chip (SoC) is challenging, due to its full-custom design methodology and use of the metal stack. Synthesizable FPGAs, built using an ASIC standard-cell methodology, have gained traction in industry and academia as a flexible alternative for embedded FPGA fabrics [1-5]. This work pertains to physical design considerations for synthesizable FPGAs, specifically those targetable by the VTR framework [1, 6]. We address the following: 1) the impact of floorplanning on the performance of, and delay variability in, the synthesized fabric; 2) extraction of component-wise delays from the standard-cell layout; 3) an examination of the spatial correlation of delays on-chip; and 4) annotation of extracted post-layout delays into VTR's timing model. In the main, this paper considers the question: in a fully synthesized standard-cell FPGA, how predictable are the delays? Our work thus contributes to the realization and modelling of high-performance standard-cell FPGA fabrics with performance predictability.