A 67dB DR 50MHz BW CT Delta Sigma modulator achieving 207 fJ/conv
A 67dB DR 50MHz BW CT Delta Sigma modulator achieving 207 fJ/conv
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67dB DR 50MHz BW CT Delta Sigma 调制器实现 207 fJ/conv
DOI：
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发表时间：
2013
期刊：
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通讯作者：
M. Ortmanns
中科院分区：
文献类型：
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作者：
John G. Kauffman;Chao Chu;J. Becker;M. Ortmanns
本文提出了一种三阶连续时间δ σ调制器，该调制器在1GHz频率下采用4位内量化器采样，过采样比为10。由于动态元件匹配在低过采样时无效，并且在高采样率时难以在环路内设计，因此可以在数字域中使用DAC线性化来校正DAC1的非线性。该调制器采用1.2V、90nm CMOS工艺实现，在50MHz带宽下，SNDR为61.7 dB， DR为67dB， SFDR为72dB。总的来说，调制器达到了207 fJ/conv的性能值。
This paper presents a third order continuous time Delta Sigma modulator with a 4 bit internal quantizer sampling at 1GHz using an oversampling ratio of 10. Since dynamic element matching is ineffective at low oversampling and difficult to design within the loop at high sampling rates, a DAC linearization can be used in the digital domain to correct for non-linearities of DAC1. The presented modulator has been realized in a 1.2V, 90nm CMOS process and achieves an SNDR of 61.7 dB, DR of 67dB and an SFDR of 72dB within a 50MHz bandwidth. Overall, the modulator achieves a figure of merit of 207 fJ/conv.