Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands

Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands
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用于无符号和有符号操作数的可变延迟推测并行前缀加法器

DOI:
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发表时间:
2016
期刊:
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
影响因子:
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通讯作者:
A. Strollo
A. Strollo
中科院分区:
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文献类型:
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作者:
D. Esposito;D. Caro;A. Strollo

文献摘要

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可变延迟加法器 (VLA) 通过推测来减少平均加法时间:精确的算术函数被近似的算术函数取代,该函数速度更快,并且在大多数情况下都能给出正确的结果。当推测失败时,错误检测和纠正电路会在下一个时钟周期中给出正确的结果。之前的论文研究了基于 Kogge-Stone、Han-Carlson 或进位选择拓扑的 VLA,推测进位传播仅涉及几个连续位。然而,在使用 2 的补码表示的一些应用中,操作数具有高斯分布,并且进位链的重要部分可以与加法器的大小一样长。在本文中,我们提出了五种新颖的 VLA 架构,基于 Brent-Kung、Ladner-Fisher、Sklansky、混合 Han-Carlson 和进位增量并行前缀拓扑。此外,我们提出了一种新的高效错误检测和纠正技术,使所提出的 VLA 适合使用 2 的补码表示的应用。为了研究 VLA 性能,已使用 UMC 65 nm 库综合了所提出的架构,操作数长度范围为 32 至 128 位。获得的结果表明,当需要高速时,所提出的 VLA 优于以前的推测架构和标准(非推测)加法器。
A variable latency adder (VLA) reduces average addition time by using speculation: the exact arithmetic function is replaced by an approximated one, that is faster and gives correct results most of the times. When speculation fails, an error detection and correction circuit gives the correct result in the following clock cycle. Previous papers investigate VLAs based on Kogge-Stone, Han-Carlson or carry select topologies, speculating that carry propagation involves only a few consecutive bits. In several applications using 2's complement representation, however, operands have a Gaussian distribution and a nontrivial portion of carry chains can be as long as the adder size. In this paper we propose five novel VLA architectures, based on Brent-Kung, Ladner-Fisher, Sklansky, Hybrid Han-Carlson, and Carry increment parallel-prefix topologies. Moreover, we present a new efficient error detection and correction technique, that makes proposed VLAs suitable for applications using 2's complement representation. In order to investigate VLAs performances, proposed architectures have been synthesized using the UMC 65 nm library, for operand lengths ranging from 32 to 128 bits. Obtained results show that proposed VLAs outperform previous speculative architectures and standard (non-speculative) adders when high-speed is required.